1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly a semiconductor memory device provided with hierarchical control signal lines.
2. Description of the Background Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a large number of sense amplifiers for amplifying minute potential differences occurring on bit line pairs are arranged in a straight line. Each sense amplifier includes a P-channel sense amplifier for raising the voltage on one of the paired bit lines to a power supply voltage, and an N-channel MOS transistor for lowering the voltage on the other bit line to a ground voltage. For operating the sense amplifier, it is required to provide a sense signal for driving the P-channel sense amplifier as well as a sense signal for driving the N-channel sense amplifier. Therefore, a sense signal line for driving the P-channel sense amplifiers and a sense signal line for driving the N-channel sense amplifiers are arranged along the large number of sense amplifiers arranged in a line. These P-channel sense amplifiers are commonly connected to the sense signal line, and all operate simultaneously in response to the sense signal. The N-channel sense amplifiers are commonly connected to the other sense signal line, and all operate simultaneously in response to the sense signal.
As described above, the conventional device is provided with the two sense signal lines arranged along the large number of sense amplifiers arranged in a line so that the device suffers from increase in layout area.
With increase in memory capacity, it may be contemplated to employ a hierarchical structure for the control signal lines, similarly to word lines and bit lines. For employing the hierarchical structure in which the control signal is hierarchically divided into a main signal line and many sub-signal lines, the length of main signal line must be increased with increase in memory capacity. Increase in length of the main signal line results in a problem that signal delay increases with increase in distance to the sub-signal line from a source of the control signal.